These images from NASA’s Solar Dynamics Observatory show four X-class flares emitted on May 12-14, 2013 – the first four X-class flares of 2013. Credit: NASA/SDO/GSFC
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This week has seen an intense period of activity from the Sun, with four colossal solar flares in 24 hours. Here on Earth, such spectacular solar displays seem far enough away but in fact these extra-terrestrial events are a cause for concern in our modern digital world.
Of concern are so called single event upsets (SEUs), which occur when high energy particles hit microelectronics, causing devices to malfunction. Solar flares and cosmic rays are the main sources of such particles, and with the ubiquitous nature and rapid advances in microelectronics, it’s an area of intense interest.
So far the particles most under scrutiny have been neutrons, generated in the Earth’s atmosphere by cosmic rays. But recently attention has turned to muons, and this week a group from Vanderbilt University and Marvell Semiconductor in the US have brought microelectronics to Port 4 at the RIKEN-RAL muon facility at ISIS, to try and understand how muons could cause these devices to fail.
Dr Nelson Tam of Marvell Semiconductor positions the hardware.
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The semiconductor industry is keen to understand the mechanisms of failure from a muon SEU, to inform future design and fabrication processes. The Vanderbilt group is working with 10 industrial collaborators, including Marvell Semiconductors, who provided some of the hardware for testing and Cisco Systems.
At present SEUs resulting from neutrons are the most dominant failure mechanisms in microelectronic devices, and up until now muons have been considered unlikely to cause significant problems. However, as microelectronic devices become smaller and more complex the risk has increased.
Current techniques mean that transistors can be fabricated with features of the order of 16nm, but to scale even further will require significant changes to transistor geometries, materials and process steps. In this project, the group exposed commercially produced Static Random Access Memory (SRAMs) devices with 28 nm nodes to the muon beam. This is the first time this kind of experiment has been attempted at ISIS. Recording the muon flux and the number of errors that occur will give the probability of muon-induced failures.
Dr. Sierawski and Prof. Bhuva from Vanderbilt University, along with Dr. Tam from Marvell Semiconductor are conducting the experiment at ISIS. Prof. Bhuva says, “The micro-electronics industry is on the verge of architectural shift as devices get to below 20 nm. It was predicted in 1979 that there will be a watershed moment when such devices become susceptible to muon ionisation, and we believe current technologies are approaching this threshold.
“Our experiments today are about understanding the probability of these events, which represents an important contribution to the semiconductor industry. This will inform future design decisions, enabling manufacturers to develop devices that are less susceptible to muon SEUs.”
Chris Frost from ISIS met the Vanderbilt team last year, and suggested they apply for time on ISIS. He says, “We’ve known about neutron SEUs for some time, and in fact ISIS are building a new instrument, CHIPPIR, for rapid testing of electronics with high energy neutrons. But the idea of doing the same kind of experiment with muons is very exciting. It’s very early days, but this is a great example of industry, academia and facilities working together on cutting edge research that could provide real tangible benefits to the semiconductor industry and everyone who relies on it.”
Research date: May 2013
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